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The 2nd Variation, named "Cascades", was based on the Pentium III "Coppermine" core. The "Cascades" Xeon utilized a 133 MT/s entrance side bus and relatively smaller 256 kB on-die L2 cache resulting in Nearly exactly the same capabilities as the Slot 1 Coppermine processors, which were capable of dual-processor Procedure but not quad-processor or